1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Related Background Art
1T-1C (1 transistor-1 capacitor) DRAMs have been used widely for years. It is becoming more and more difficult to reduce the cell size of these 1T-1C DRAMs. Under the circumstances, semiconductor devices with new structures are in demand.
On the other hand, development of system LSIs incorporating a semiconductor storage device such as DRAM and a logic LSI is progressing. In a manufacturing process of a DRAM-incorporated system LSI, it is desirable that the manufacturing process of the progressive high-speed logic LSI and the manufacturing process of DRAM match well.
From this point of view, a FBC cell (floating body transistor cell) has been reported. The FBC cell is a semiconductor storage device based on a 1T-1C DRAM, and an article on it is found in “Memory Design Using One-Transistor Gain Cell on SOI” (T. Ohsawa et al., ISSCC2002, Lecture No. 9.1). FIGS. 16 through 18 show the structure of this FBC cell.
FIG. 16 is a plan view of a part of a FBC cell. Bit lines BL extend latitudinally when viewed in FIG. 16. Under the bit lines BL, word lines WL and source lines SL extend longitudinally when viewed in FIG. 16 (vertically with respect to the bit lines BL).
FIG. 17 is a cross-sectional view taken along the X—X line (word lines WL) of FIG. 16. The bit lines BL are electrically connected by BL contacts to N-type diffusion layers 2 lying on a surface region of the semiconductor substrate. The word lines WL are electrically insulated by a gate insulation film 5 from P-type diffusion layers 6 lying in the surface region of the semiconductor substrate. The source lines SL are electrically connected to N-type diffusion layers 4 lying in areas opposite from the N-type diffusion layers 2 with respect to the word lines WL. Thus formed are MOS transistors each having a word line WL as its gate electrode and a bit line BL as its drain electrode.
The surface region 10 of the semiconductor substrate is composed of an alternately adjacent alignment of the N-type diffusion layers 2, 4 and the P-type diffusion layers 6. The surface region 10 of the semiconductor substrate is insulated by an insulation layer 20 from an N+-type diffusion layer 30 and a P substrate 40 underlying the insulation layer 20 to form a SOI structure.
FIG. 18 is a cross-sectional view taken along the Y—Y line (word lines WL) of FIG. 16. The word lines WL extend under the bit lines BL, and the P-type diffusion layers 6 extend below the word lines WL via the gate insulation film 5. In this cross-sectional view, each P-type diffusion layer 6 is surrounded by a gate insulation film 5, CAP insulation layer 12 and an insulation layer 20 that are made of insulating materials.
N+-type polysilicon pillars 50 are formed to extend from the CAP insulation layers 12 near the P-type diffusion layers 6 through the insulation layer 20 and reach the N+-type type diffusion layer 30. Distance from each N+-type polysilicon pillar 50 to a nearest P-type diffusion layer 6 is much shorter than the distance from the N+-type diffusion layer 30 to the P-type diffusion layer 6. Therefore, capacitance between the N+-type diffusion layer 30 and the P-type diffusion layer 6 becomes much larger than the capacitance in a structure without the N+-type polysilicon pillar 50.
This semiconductor storage device operates as explained below.
As shown in FIG. 17, each MOS transistor having a word line WL as its gate electrode and a bit line BL as its drain electrode permits a current to flow between the word line WL and an associated source line SL when a positive voltage is applied to the word line WL. This current causes impact ionization, and positive and negative electric charges are produced in the P-type diffusion layer 6. At that time, a negative voltage is applied to the N+-type diffusion layer 30 and the N+-type polysilicon pillar shown in FIG. 18, and holes are stored in the P-type diffusion layer 6.
After that, when the voltage applied to the word line WL is changed to a negative voltage, a reverse bias is applied to PN junctions between the P-type diffusion layer 6 and the N-type diffusion layers 2, 4. Therefore, holes are retained in the P-type diffusion layer 6 even after the MOS transistor is turned OFF. As a result, data are retained in the semiconductor storage device.
In this semiconductor storage device, since the capacitance between each P-type diffusion layer 6 and the N+-type diffusion layer 30 is increased by forming the N+-type polysilicon pillar 50 near the P-type diffusion layer 6, a larger quantity of holes can be retained in the P-type diffusion layer 6.
This semiconductor storage device uses a SOI substrate. There are SIMOX and bonding techniques as manufacturing methods of SOI substrates.
The SIMOX technique injects oxygen ions from a surface of a silicon substrate to a depth of approximately 100 nm to 500 nm. The ion injection invites crystalline defects in the SOI portion formed along the surface region of the semiconductor substrate. Individual memory cells of the FBC cell are very small. Hence, even a slight increase of junction leakage by small crystalline defects may cause incorrect operations of the semiconductor storage device.
In case of the bonding technique, there is a limit to thinning the BOX layer (corresponding to the insulating layer 20). This involves the problem that thinning the BOX layer beyond a certain extent is technically difficult and that the BOX layer must be thick to a certain extent in the peripheral logic circuit portion of the system LSI.
That is, if the bonding technique is used, thickness of the BOX layer is technically limited from 100 nm to 150 nm at minimum.
In order to further increase the capacitance between each P-type diffusion layer 6 and the N+-type diffusion layer 30 in the system LSI, the BOX layer (insulating layer 20) under the FBC cell portion had better be thinner. The peripheral logic circuit portion, however, requires a BOX layer of a certain thickness to prevent capacitive coupling between the silicon substrate under the BOX layer and circuit elements. Therefore, in the system LSI, performance of the FBC cell and performance of the peripheral logic circuit portion are in a trade-off relationship with regard to thickness of the BOX layer. Though not impossible, it is not practical because of a high cost to form a BOX layer locally varying in thickness by the bonding technique.
There is therefore a demand for an inexpensive semiconductor device which has less crystalline defects along the surface region of the semiconductor substrate for making elements thereon and which is capable of reliably holding data, and a method for reliably manufacturing the semiconductor device.